Relationship between Silicon Via Size and Chip Impedance and Frequency Response in Semiconductor 3D Stacked TSV Technology

Dengyi Shang

doi:10.47297/taposatWSP2633-456911.20260705

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Relationship between Silicon Via Size and Chip Impedance and Frequency Response in Semiconductor 3D Stacked TSV Technology

7卷第5期

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Relationship between Silicon Via Size and Chip Impedance and Frequency Response in Semiconductor 3D Stacked TSV Technology
Relationship between Silicon Via Size and Chip Impedance and Frequency Response in Semiconductor 3D Stacked TSV Technology
School of Microelectronics, Nanjing University of Science and Technology, Nanjing, Jiangsu, 210014, China
2026年7卷第5期页码：52-60
网络首发：2026-07-15，

纸质出版：2026-05-30
DOI：10.47297/taposatWSP2633-456911.20260705
Accepted：

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Dengyi Shang. (2026). Relationship between Silicon Via Size and Chip Impedance and Frequency Response in Semiconductor 3D Stacked TSV Technology. 科技理论与实践（英文版）, 7(5), 52-60.

Shang Dengyi.Relationship between Silicon Via Size and Chip Impedance and Frequency Response in Semiconductor 3D Stacked TSV Technology[J].Theory and Practice of Science and Technology,2026,07(05):52-60.
Dengyi Shang. (2026). Relationship between Silicon Via Size and Chip Impedance and Frequency Response in Semiconductor 3D Stacked TSV Technology. 科技理论与实践（英文版）, 7(5), 52-60. DOI： 10.47297/taposatWSP2633-456911.20260705.

Shang Dengyi.Relationship between Silicon Via Size and Chip Impedance and Frequency Response in Semiconductor 3D Stacked TSV Technology[J].Theory and Practice of Science and Technology,2026,07(05):52-60. DOI： 10.47297/taposatWSP2633-456911.20260705.

摘要

Abstract

In three-dimensional integration technology

the geometry of through-silicon vias (TSVS) directly affects the impedance characteristics and high-frequency response of the chip. This paper systematically analyzes the mapping relationship between key size parameters such as TSV diameter

height

insulation thickness

and spacing

and equivalent electrical parameters (R

and establishes an extensible distributed parameter equivalent circuit model. Verified by comparison with the full-wave electromagnetic simulation (HFSS) in the 0-40 GHz band

the proposed model has an S-parameter error of less than 5% below 30 GHz and a maximum characteristic impedance error of 6.2%. The study shows that an increase in TSV diameter reduces resistance and inductance

but increases parasitic capacitance. Although an increase in the thickness of the insulating layer can reduce capacitance

it may weaken the substrate isolation effect. Based on this

this paper proposes an optimized design strategy based on characteristic impedance matching

defines the cost function

builds a feasible domain table through parameter scanning

and presents a reproducible design case (diameter 20 μm

insulation layer 0.25 μm

spacing 45 μm

achieving 50 Ω±3 Ω impedance). The results provide a theoretical basis and practical approach for the electrical design of TSVS in three-dimensional integrated circuits.

关键词

Keywords

references

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