High-Reliability Design Based on Bit-Level Repair Techniques

Yaxing Zhou; Ao Shen

doi:10.47297/taposatWSP2633-456919.20250605

PDF
导出
分享
收藏
专辑

High-Reliability Design Based on Bit-Level Repair Techniques

6卷第5期

浏览量: 0 Downloads: 0

High-Reliability Design Based on Bit-Level Repair Techniques
High-Reliability Design Based on Bit-Level Repair Techniques
Zhejiang Hikstor Technology Co., Ltd., Hangzhou, Zhejiang, China, 311300
2025年6卷第5期页码：94-99
纸质出版日期：2025-05-19
DOI：10.47297/taposatWSP2633-456919.20250605
Accepted：

Scan QR Code

(2025). High-Reliability Design Based on Bit-Level Repair Techniques. 科技理论与实践（英文版）, 6(5), 94-99.

Zhou Yaxing,Shen Ao.High-Reliability Design Based on Bit-Level Repair Techniques[J].Theory and Practice of Science and Technology,2025,06(05):94-99.
(2025). High-Reliability Design Based on Bit-Level Repair Techniques. 科技理论与实践（英文版）, 6(5), 94-99. DOI： 10.47297/taposatWSP2633-456919.20250605.

Zhou Yaxing,Shen Ao.High-Reliability Design Based on Bit-Level Repair Techniques[J].Theory and Practice of Science and Technology,2025,06(05):94-99. DOI： 10.47297/taposatWSP2633-456919.20250605.

摘要

Abstract

Traditional memory technologies are gradually difficult to meet the demands of high-reliability applications such as automotive electronics and aerospace systems. Spin-transfer torque magnetic random-access memory (STT-MRAM) has emerged as a promising alternative due to its fast read/write speed

high endurance

and full compatibility with CMOS processes. However

the unique physical properties of STT-MRAM pose challenges including hard errors (e.g.

shorts) and various types of soft errors. To address these issues

this paper proposes a high-reliability design based on bit-level repair

allowing defective bits to be repaired through dedicated conversion circuits. This approach supports both hard errors repair prior to chip fabrication and real-time repair during the product's operational lifetime

With minimal redundancy and low design complexity

the proposed method significantly improves device endurance and yield.

关键词

Keywords

references

Xue C J, Zhang Y, Chen Y, et al. Emerging non-volatile memories: Opportunities and challenges[C]//Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. 2011: 325-334.

osomi M, Yamagishi H, Yamamoto T, et al. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM[C]//IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE, 2005: 459-462.

Kent A D, Worledge D C. A new spin on magnetic memories[J]. Nature nanotechnology, 2015, 10(3): 187-191.

PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS, JESD92, Aug. 2003 .

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES, JEP122, Sep. 2016 .

Wu E Y, et al. Experimental evidence of TBD power-law for voltage dependence of oxide breakdown in ultrathin gate oxides. IEEE Trans. Electron Devices, 2002, 49(12): 2244–2253.

Hiraiwa A, Ishikawa D. Comprehensive thickness-dependent power-law of breakdown in CMOS gate oxides. IRPS 2006: 617–618.

文章被引用时，请邮件提醒。

Submit

A review of the design of multifunctional light load evtol mechanical structures

Related Author

Qiang Li School of Civil Engineering and Transportation, South China University of Technology

Related Institution

School of Civil Engineering and Transportation, South China University of Technology

⁰