Research Progress and Challenges of Signal Processing and Chip Implementation for Non-Invasive Brain-Computer Interface

Zenghao Liang

doi:10.47297/taposatWSP2633-456931.20260708

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Research Progress and Challenges of Signal Processing and Chip Implementation for Non-Invasive Brain-Computer Interface

7卷第8期

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Research Progress and Challenges of Signal Processing and Chip Implementation for Non-Invasive Brain-Computer Interface
Research Progress and Challenges of Signal Processing and Chip Implementation for Non-Invasive Brain-Computer Interface
Zhuhai Oriental Foreign Language Experimental School, Zhuhai, Guangdong, 519060, China
2026年7卷第8期页码：157-161
纸质出版：2026-08-30
DOI：10.47297/taposatWSP2633-456931.20260708
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Zenghao Liang. (2026). Research Progress and Challenges of Signal Processing and Chip Implementation for Non-Invasive Brain-Computer Interface. 科技理论与实践（英文版）, 7(8), 157-161.

Liang Zenghao.Research Progress and Challenges of Signal Processing and Chip Implementation for Non-Invasive Brain-Computer Interface[J].Theory and Practice of Science and Technology,2026,07(08):157-161.
Zenghao Liang. (2026). Research Progress and Challenges of Signal Processing and Chip Implementation for Non-Invasive Brain-Computer Interface. 科技理论与实践（英文版）, 7(8), 157-161. DOI： 10.47297/taposatWSP2633-456931.20260708.

Liang Zenghao.Research Progress and Challenges of Signal Processing and Chip Implementation for Non-Invasive Brain-Computer Interface[J].Theory and Practice of Science and Technology,2026,07(08):157-161. DOI： 10.47297/taposatWSP2633-456931.20260708.

摘要

Abstract

Non-invasive scalp-EEG brain-computer interfaces (BCIs) are moving from lab to wearable products but face low SNR

high power

poor real-time decoding

and insufficient integration. The core contradiction is weak (1–100 µV)

artifact-contaminated signals versus low-power

miniaturized

high-throughput on-chip processing. This paper reviews the full-stack technical framework—preprocessing

feature extraction

and intelligent decoding—and summarizes dedicated SoC architectures and key circuit innovations. It identifies multi-dimensional bottlenecks at algorithm and hardware layers and proposes three progressive development paths: lightweight embedded processing

multi-channel integrated chips

and hardware-algorithm co-optimized closed-loop systems. Quantitative comparisons using mainstream wearable EEG chip cases verify that only when noise suppression

decoding latency

and power consumption jointly reach threshold values can non-invasive BCI achieve long-term stable wearable operation without external computing. This study provides theoretical and quantitative decision support for R&D and industrial transformation.

关键词

Keywords

references

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